WSEAS Transactions on Signal Processing


Print ISSN: 1790-5052
E-ISSN: 2224-3488

Volume 13, 2017

Notice: As of 2014 and for the forthcoming years, the publication frequency/periodicity of WSEAS Journals is adapted to the 'continuously updated' model. What this means is that instead of being separated into issues, new papers will be added on a continuous basis, allowing a more regular flow and shorter publication times. The papers will appear in reverse order, therefore the most recent one will be on top.


Analysis and VLSI High Speed of Parallel Causal EBCOT Architecture for Image Compression

AUTHORS: Refka Ghodhbane, Taoufik Saidani, Layla Horrigue, Mohamed Atri

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ABSTRACT: Embedded block coding with optimized truncation (EBCOT) is a key algorithm in digital cinema (DC) distribution system. Though several high speed EBCOT architectures exist, all are not capable of meeting the DC specifications. With the augmentation in multimedia technology, demand for high speed real time image compression system has also increased. JPEG2000 is a relatively new image compression standard which builds and improves on its predecessor JPEG. In Jpeg 2000 the embedded Block Coding with Optimal Truncation (EBCOT) is the most important element to calculate the very hard portion in the compressing process of JPEG 2000 image compression standard. This paper proposes a Parallel Bit Plane Coding (BPC) architecture in which three coding passes operate in parallel and are allowed to progress independently.

KEYWORDS: EBCOT, JPEG2000, VHDL, FPGA, VLSI

REFERENCES:

[1] JPEG 2000 image coding system, ISO/IEC International Standard 15444 1.ITURecommendationT.800, (2000).

[2] ISO/IEC JTC1/SC29/WG1 N2678, document JPEG 2000 Part 1 020719 (final publication draft), (2002).

[3] D. S. Taubman and M. W. Marcellin.JPEG2000 Image Compression Fundamentals, Standards, and Practice (2002).

[4] T. Acharya and P. Tsai, JPEG2000 Standard for Image Compression: Concepts, Algorithms and VLSI Architectures, (2005).

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[6] M. Rabbani and R. Joshi, An overview of the JPEG 2000 still image compression standard, Signal Processing: Image Communication., 17(1) (2002) 3–48.

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[8] A. Das, A. Hazra, and S. Banerjee, An efficient architecture for 3-D discrete wavelet transform, IEEE Trans. Circuits System Video Technology, 20(2) (2010) 286–296.

[9] K. Liu, Y. Zhou, Y. Song Li, and J. F. Ma, A high performance MQ encoder architecture in JPEG2000,Integrarion, the VLSI Journal, 43(3)( 2010)305–317.

[10] JASPER software reference manual. ISO/IEC/JT.

[11] R. Wintner, Bits on the big screen, IEEE Spectrum, vol. 43,no. 12, pp. 42–48, 2006..

[12] Digital Cinema Initiatives, LLC Member Representatives Committee: Digital Cinema System Specification V1.0, Final Approval, July 2005..

[13] Digital Cinema Initiatives, LLC Member Representatives Committee: Digital Cinema System Specification V1.2, March 2008..

[14] Sarawadekar. K, Banerjee.S, A highperformance architecture of JPEG 2000 and its FPGA Implementation. In 17th European Signal Processing conference (EUSIPCO 2009), Septembre 2009.

[15] Gangadhar.M, Bhatia.D, FPGA based EBCOT arcitecture for JPEG 2000. Microprocess. Microsyst.29(8-9), 363-373(2005).

WSEAS Transactions on Signal Processing, ISSN / E-ISSN: 1790-5052 / 2224-3488, Volume 13, 2017, Art. #11, pp. 90-96


Copyright © 2017 Author(s) retain the copyright of this article. This article is published under the terms of the Creative Commons Attribution License 4.0

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