Login



Other Articles by Author(s)

Subhash Patel
Rajesh A. Thakker



Author(s) and WSEAS

Subhash Patel
Rajesh A. Thakker


WSEAS Transactions on Circuits and Systems


Print ISSN: 1109-2734
E-ISSN: 2224-266X

Volume 16, 2017

Notice: As of 2014 and for the forthcoming years, the publication frequency/periodicity of WSEAS Journals is adapted to the 'continuously updated' model. What this means is that instead of being separated into issues, new papers will be added on a continuous basis, allowing a more regular flow and shorter publication times. The papers will appear in reverse order, therefore the most recent one will be on top.


Volume 16, 2017



An Efficient Artificial Bee Colony Algorithm and Analog Circuit Design Environment

AUTHORS: Subhash Patel, Rajesh A. Thakker

Download as PDF

ABSTRACT: The artificial bee colony algorithm (ABC), a population based algorithm, provides solutions with better accuracy compared to other competitive population based algorithms. However, it suffers from slow convergence speed. We suggest modifications in search strategy of ABC to improve overall performance and named this modified algorithm, Efficient ABC algorithm (EABC). The performance of EABC is compared with ABC by conducting experiment on 15 well-known scalable benchmark functions and synthesizing two analog circuits, two stage opamp and bulk driven OTA, in 130 m CMOS technology. The proposed algorithm is performing significantly better than ABC for 14 benchmark functions and for remaining one the results are comparable. With the two-stage op-amp design problem, the average design error is 0.4% with EABC compared to 2.10% with ABC. Not only that the average design time is only 19.8 minutes with EABC in contrast to 22 minutes with ABC. In case of bulk driven OTA design, the average design error with EABC algorithm is zero compared to 1.26% with ABC. The average design time taken to design bulk driven OTA by EABC is only 4.62 minutes compared to 9.07 minutes with ABC. Apart from this, EABC is also compared with GABC and MABC algorithms, the variants of ABC. This comparison clearly indicates that EABC is performing better than ABC, GABC and MABC.

KEYWORDS: Artificial bee colony, Optimization, Automatic circuit design, Operational Amplifier, OTA

REFERENCES:

[1] S. Sivanandam and S. Deepa, Introduction to genetic algorithms. Springer Science & Business Media, 2007.

[2] J. Kennedy and R. Eberhart, “Particle swarm optimization,” in Neural Networks, 1995. Proceedings., IEEE International Conference on, vol. 4, pp. 1942–1948 vol.4, Nov 1995.

[3] M. Dorigo and C. Blum, “Ant colony optimization theory: A survey,” Theoretical computer science, vol. 344, no. 2, pp. 243–278, 2005.

[4] D. Simon, “Biogeography-based optimization,” Evolutionary Computation, IEEE Transactions on, vol. 12, no. 6, pp. 702–713, 2008.

[5] D. Karaboga and B. Basturk, “A powerful and efficient algorithm for numerical function optimization: artificial bee colony (abc) algorithm,” Journal of global optimization, vol. 39, no. 3, pp. 459–471, 2007.

[6] D. Karaboga and B. Basturk, “On the performance of artificial bee colony (abc) algorithm,” Applied soft computing, vol. 8, no. 1, pp. 687– 697, 2008.

[7] D. Karaboga and B. Akay, “A comparative study of artificial bee colony algorithm,” Applied Mathematics and Computation, vol. 214, no. 1, pp. 108–132, 2009.

[8] K. Sundareswaran, P. Sankar, P. Nayak, S. P. Simon, and S. Palani, “Enhanced energy output from a pv system under partial shaded conditions through artificial bee colony,” Sustainable Energy, IEEE Transactions on, vol. 6, no. 1, pp. 198–209, 2015.

[9] R. A. Vural, T. Yildirim, T. Kadioglu, and A. Basargan, “Performance evaluation of evolutionary algorithms for optimal filter design,” Evolutionary Computation, IEEE Transactions on, vol. 16, no. 1, pp. 135–147, 2012.

[10] D. Karaboga and C. Ozturk, “A novel clustering approach: Artificial bee colony (abc) algorithm,” Applied soft computing, vol. 11, no. 1, pp. 652– 657, 2011.

[11] M. Ma, J. Liang, M. Guo, Y. Fan, and Y. Yin, “Sar image segmentation based on artificial bee colony algorithm,” Applied Soft Computing, vol. 11, no. 8, pp. 5205–5214, 2011.

[12] M. Sonmez, “Artificial bee colony algorithm for optimization of truss structures,” Applied Soft Computing, vol. 11, no. 2, pp. 2406–2418, 2011.

[13] X. Zhang, X. Zhang, S. Ho, and W. Fu, “A modification of artificial bee colony algorithm applied to loudspeaker design problem,” Magnetics, IEEE Transactions on, vol. 50, pp. 737–740, Feb 2014.

[14] G. Nicosia, S. Rinaudo, and E. Sciacca, “An evolutionary algorithm-based approach to robust analog circuit design using constrained multiobjective optimization,” Knowledge-Based Systems, vol. 21, no. 3, pp. 175–183, 2008.

[15] M. Barros, J. Guilherme, and N. Horta, “Analog circuits optimization based on evolutionary computation techniques,” INTEGRATION, the VLSI journal, vol. 43, no. 1, pp. 136–155, 2010.

[16] R. A. Thakker, M. S. Baghini, and M. B. Patil, “Automatic design of low-power lowvoltage analog circuits using particle swarm optimization with re-initialization,” Journal of Low Power Electronics, vol. 5, no. 3, pp. 291–302, 2009.

[17] G. Zhu and S. Kwong, “Gbest-guided artificial bee colony algorithm for numerical function optimization,” Applied Mathematics and Computation, vol. 217, no. 7, pp. 3166–3173, 2010.

[18] W. f. Gao and S. y. Liu, “A modified artificial bee colony algorithm,” Computers & Operations Research, vol. 39, no. 3, pp. 687–697, 2012.

[19] P. Allen and D. Holberg, CMOS Analog Circuit Design. OUP USA, 2012.

[20] B. Blalock and P. Allen, “A low-voltage, bulkdriven mosfet current mirror for cmos technology,” in Circuits and Systems, 1995. ISCAS ’95., 1995 IEEE International Symposium on, vol. 3, pp. 1972–1975 vol.3, Apr 1995.

[21] B. Blalock, P. Allen, and G. Rincon-Mora, “Designing 1-v op amps using standard digital cmos technology,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 45, pp. 769–780, Jul 1998.

[22] R. He and L. Zhang, “Evaluation of modern mosfet models for bulk-driven applications,” in Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on, pp. 105–108, Aug 2008.

[23] J. Carrillo, G. Torelli, R. Perez-Aloe, and J. Duque-Carrillo, “1-v rail-to-rail bulk-driven cmos ota with enhanced gain and gainbandwidth product,” in Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on, vol. 1, pp. I/261–I/264 vol. 1, Aug 2005.

WSEAS Transactions on Circuits and Systems, ISSN / E-ISSN: 1109-2734 / 2224-266X, Volume 16, 2017, Art. #13, pp. 108-122


Copyright © 2017 Author(s) retain the copyright of this article. This article is published under the terms of the Creative Commons Attribution License 4.0

Bulletin Board

Currently:

The editorial board is accepting papers.


WSEAS Main Site