AUTHORS: Yurin Jin, Seongik Cho, Minwoong Lee
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ABSTRACT: A successive approximation register(SAR) analog-to-digital converter(ADC) is widely used because of its relatively short conversion time and small size. However, a SAR ADC requires a DAC of the same resolution, resulting in a larger area. To solve this problem, a DAC that does not increase in area as resolution increases is needed. This paper presents SAR ADC and DAC using Switched Capacitor(SC) integrator. This DAC 's area is independent of resolution and ADC is no need to a sample and hold circuit because it uses an SC integrator. The operation of this ADC is similar to a charge-redistribution based SAR ADC. The reference voltage is generated by charge redistribution of the SC integrator input capacitor and the reference capacitor, and the DAC voltage is generated by accumulating the generated voltage on the output capacitor of the SC integrator. The proposed SAR ADC was designed using TSMC 0.18μm CMOS high voltage technology, occupies on chip area of 0.316mm2. At 5V supply and 100kS/s, the simulated SNDR and ENOB are 53.7dB and 8.63bit. Considering the good DNL, a higher resolution ADC can be designed with the same area.
KEYWORDS: Analog-to-digital converter, Successive approximation register, Switched Capacitor integrator, SAR ADC, Digital-to-Analog converter, Charge-redistribution based SAR ADC, Sample and Hold circuit
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